clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, HSIO, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

Tcl, C, Python, Perl, Shell, System Verilog Assertions, Uvm, Emulation, systemverilog, Formal

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design

Shell, Perl, Python, Tcl, Test Cases, Cadence Xcelium, Mentor QuestaSim, Synopsys VCS, Constrained Random Verification, Functional Verification, PCI Express PCIe protocol, ASIC SoC Design Verification, Functional Coverage Models, Verification Plans, Waveform analysis, Assertion-Based Verification SVA, Simulation Tools, SystemVerilog UVM, Testbenches, Assertions

C, Tcl, Python, Pcie, Perl, Universal Verification Methodology, USB2, HSIO PHY Controllers, systemverilog, UFS, MIPI, Open Verification Methodology, USB3, Skill

Tcl, Python, Perl, SVA, Uvm, Functional Coverage, ASIC SoC Subsystem IP verification, systemverilog