Debugging, Software testing acceleration, Emulation, Zebu, Veloce, Hardware design validation, Palladium

lauterbach , Spi, C, Systemc, Usb, Shell, Tcl, Verilog, Jtag, Python, Pcie, Perl, DDR, Axi, Coresight, LPDDR, RTL, UltraSoC, Cadence Palladium, systemverilog, VHDL, Cadence Palladium XP, ZeBu

model design , Eda, Programming Languages, Technical Documentation, Integration, architecture and design tools, Synthesis, Place And Route, circuit specifications, layout flow, logic designs, scripting tools, ASIC Design, custom circuit design, Verification, design verification methods, RTL to GDS Flow, virtuoso, system simulations, Validation, IP block SoC development

Python Scripting, System Verilog, BFM models, GPU emulation

Perl, Verilog, Python, Tcl, Cadence Xcelium, Palladium, Rtl Design, Synopsys VCS, VHDL, Zebu, SoC Verification, Velloce

clocking , Verilog, System Verilog, SOC Emulation, SOC boot flow, Power management flows, Synthesis, PNR, FPGA based prototyping platforms, Low Power Verification, System Verilog Assertions, RTL GLS level simulations, Platform bring up in Emulators or Silicon, Emulation platforms, Functional Verification, Timing Analysis

FPGA Design, Python Scripting, Soc Architecture, Test Automation, systemverilog, Verification Methodology, Hardware Debugging, Signal Integrity, Performance Analysis, Emulation Tools

Tcl, Python, Shell, Soc Architecture, Rtl Design, UVM verification flows, Linux environments, Siemens Veloce, Synopsys ZeBu, systemverilog