Logic Design, DDR, AMS verification, system level design, Mixed Signal IP design, AMS design techniques, High-speed circuits, Lab debugs on AMS IPs, Tx Rx CTLE Amplifiers Samplers, Analog Mixed Signal design, HBM technologies, Circuit architecture, SERDES

Unix Shell, System Verilog, Perl, Automated flows, Uvm, Gate Level Simulations, formal verification, Design Verification, NoCs, Interconnects

System Verilog, Uvm, Environment Development, Design Verification, Functional Verification, Test Plan Generation

System Design, Design Verification