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Solidworks, STAAD.Pro, Autocad, Sketchup
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canape , Aspice, Requirement Analysis, CANcase, Canoe, Software Requirements Specification, DLT, Technical Safety Requirements, HIL, DDS, Functional Safety Requirements, ISO 26262, ADAS features
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account leadership
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Verilog, Microprocessors, Usb, Pcie, LINT, cdc, SoC clocking, pad ring, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, System-Verilog, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, timing concepts for ASIC, APB, Timing Closure, SoC design and integration, AHB, Multi Clock designs
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Ms Excel, VAT e-invoicing, Audits over financial reporting, Accounts receivable, Data analysis tools, AI tools and technologies, Travel supplier pricing contracts, Card payment operations, Rebate structures
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Tcl Scripting, Python, Interface closure, SDC constraints, Path-based debugging, primetime, Hierarchical timing models, Tempus, MCMM timing analysis, Advanced-node timing effects, Timing ECO generation
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production orders , Sap Pp, Sap Mm, Uat, Routing, Sit, Bom, Production Planning, Work Centers, MRP, Capacity Planning, hypercare support
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Last Updated: 13-10-2026 10:44:53 PM