VTL Design & Verification Engineer

e are seeking a skilled Verification Engineer to join our team. The successful candidate will be responsible for the verification of internally developed VTLs (Veloce-friendly standard protocols such as AMBA, PCIe, SAS, Ethernet, MIPI, etc.) using various standard verification methodologies, including UVM, and ensuring signoff based on coverage matrix.

Responsibilities

Develop verification environments using the standard verification methodologies for protocols like PCIe, SAS, SATA, etc.

Implement IP-level verification to ensure 100% functional and code coverage. Suggest and prototype various verification flows using Veloce.

Integrate and qualify various VTLs with Questa-based Verification IPs.

Apply customer use models within internal test suites, which may require interfacing with customers and occasional travel to customer sites.

Automate and enhance methodology suites to improve verification efficiency and productivity. .

Qualifications:

• We seek a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/VLSI from top reputed Engineering colleges with 4-8 years of significant experience in software development. Experience in EDA will be a phenomenal plus!
• We value you practical experience with any of the following protocols: AMBA, PCI/PCIe, SAS, Ethernet, MIPI.
• Experience in IP and SOC level verification.
• Proficiency of verification methodologies such as Specman, SV, UVM, OVM, TLM, Assertion, Coverage, co-simulation, and co-verification. FPGA/Emulation experience is helpful.
• Strong scripting and automation knowledge is a significant plus!
• Good interpersonal skills for working with external interfaces.
• Good problem solving and analytical skills.
• The person should be self-motivated and can work independently.