Role Overview
We are seeking an experienced VLSI EDA Engineer with strong expertise in RTL front-end methodology and proficiency in RTL simulation and analysis tools. The ideal candidate will play a key role in enabling design teams with robust EDA flows, ensuring high-quality RTL development and verification.
Key Responsibilities
- Develop, maintain, and enhance RTL front-end methodologies for ASIC/SoC design.
- Support design teams in RTL simulation using tools such as Synopsys VCS, Cadence Xcelium, and debug environments like Verdi.
- Perform RTL quality checks including:
- Lint analysis for coding style and structural integrity.
- Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis for functional correctness.
- Automate and optimize EDA flows for improved efficiency and scalability.
- Collaborate with design and verification teams to resolve RTL issues and improve design quality.
- Provide documentation, training, and support for EDA tools and methodologies.
Required Skills & Qualifications
- Bachelor's/Master's degree in Electrical Engineering, Electronics, or related field.
- 6+ years of experience in VLSI design and EDA methodologies.
- Strong knowledge of RTL design principles and front-end flows.
- Hands-on experience with:
- Simulation tools: Synopsys VCS, Cadence Xcelium.
- Debug tools: Verdi or similar.
- RTL analysis tools: SpyGlass or equivalent for Lint, CDC, RDC checks.
- Proficiency in scripting languages (Perl, Python, Shell, TCL) for flow automation.
- Excellent problem-solving skills and ability to work in cross-functional teams.
Preferred Skills
- Familiarity with UPF/Power intent checks.
- Exposure to formal verification and static timing analysis concepts.
- Experience in EDA tool evaluation and benchmarking.
Soft Skills
- Strong communication and collaboration skills.
- Ability to work independently and mentor junior engineers.
- Detail-oriented with a focus on quality and efficiency.
