Job Title: Senior / Lead IP Verification Engineer
Experience: 8+ Years
Location: Bangalore / Hyderabad / Pune / Noida (or as applicable)
Job Description
We are looking for a highly experienced IP Verification Engineer with 8+ years of handson experience in endtoend verification of complex digital IPs. The role involves ownership of verification strategy, architecture understanding, testbench development, coverage closure, and mentoring junior engineers across highperformance SoC/IP programs.
Key Responsibilities
- Own endtoend verification of complex IPs from spec review to signoff.
- Define verification strategy and test plans aligned with architecture and requirements.
- Develop scalable UVMbased verification environments from scratch.
- Drive constrainedrandom testing, functional coverage, and coverage closure.
- Develop assertionbased verification (SVA) for protocol, interface, and architectural checks.
- Verify IPs across multiple configurations, modes, and corner cases.
- Perform deep debug of complex functional issues using waveform and coverage analysis.
- Collaborate closely with architecture, design, software, and validation teams.
- Review code, testbenches, and mentor junior verification engineers.
- Support IP reuse and SoC integration verification.
- Ensure verification signoff criteria including functional, code, and assertion coverage are met.
Required Technical Skills
Verification & Languages
- Strong expertise in SystemVerilog and UVM
- Excellent knowledge of functional coverage, scoreboards, and checkers
- Handson experience with SVA (SystemVerilog Assertions)
Protocols / IP Experience (One or More)
- AMBA protocols: AXI, AHB, APB, ACE, CHI
- Highspeed interfaces: PCIe / CXL / USB / Ethernet (as applicable)
- Subsystems/IPs:
- Interconnect / NoC
- DMA / IOMMU / MMU
- Memory controllers
- CPU or acceleratoradjacent IPs
Tools & Environment
- Simulators: VCS / Xcelium / Questa
- Debug: Verdi / DVE
- Version control: Git / Perforce
- Scripting: Python / Perl / Shell (good to have)
Leadership & Ownership (Senior Level Expectations)
- Lead verification task planning and execution
- Guide junior engineers and review deliverables
- Participate in architecture and design reviews
- Identify verification risks early and propose mitigation plans
- Contribute to process improvements and best practices
Good to Have
- Experience with SoClevel integration verification
- Exposure to formal verification (Jasper)
- Experience in lowpower verification (UPF)
- Knowledge of functional safety (ISO 26262) or security features
- Experience in postsilicon validation support
Education
- B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, or Computer Engineering
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