Verification - Cache Coherence

• ASIC design verification experience 8 to 12 years.
• Verification of high performance x86-core ISA features
• Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor.
• Development of detailed test plans and driving the execution of test plan, including functional coverage.
• Understanding the existing test bench setup and look for opportunities to improve the existing test bench.
• Adhering to coding guideline practices, develop and implement code review process.
• Collaborate with global design verification teams and drive effectively the execution of the verification plans.
• Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

PREFERRED EXPERIENCE:

• Strong understanding the design and verification life cycle.
• Hands on verification experience with C/C++/SystemVerilog testbench development.
• Hands on experience with coverage planning, coding and coverage closure.
• Experience with x86, ARM or any other industry standard microprocessor ISA.
• Experience with Cache, Coherency and Data-Consistency verification.
• Experience in clocking, reset, power-up sequences and power management verification.
• Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.
• Understanding of low power design verification techniques is a plus.