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Testchip/SOC DV Engineer

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Job Description



WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.




MTS SILICON DESIGN ENGINEER

THE ROLE:
The ideal candidate will get to work on Verification of SOC with complex Analog Mixed Signal IPs (with significant Digital and Analog content)

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

  • Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions
  • Expertise in code and functional coverage,
  • Excellent Problem solving and debugging skills.
  • Excellent Communication skills
  • Strong digital design knowledge, SoC design flow
  • Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage.
  • UPF based RTL low power verification
  • Prior experience in working on SOCs with mixed signal IPs will be helpful.

    KEY RESPONSIBILITIES:
  • Verification of SOC RTL : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification
  • Development and verification of post-si validation sequences using C/C++
  • Create methodology-based (UVM) verification testbenches and components from scratch at SOC level along with re-usability of IP level components.
  • Experienced with Verilog, System Verilog, and C or C++
  • Good understanding of JTAG protocol
  • Quality deliverables through regressions
  • Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness
  • Reviews, and feedback to design/architecture teams.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-PM2




Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.

About Company

Xilinx, Inc. was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array and creating the first fabless manufacturing model.

Job ID: 144481963