Test Engineer

Senior DFT Engineer | 6+ Years | Bangalore

Location: Bangalore

Experience: 6+ Years

Role: Senior DFT Engineer / DFT Lead

Job Summary

We are looking for an experienced DFT Engineer with 6+ years of hands-on experience in ASIC/SoC Design-for-Test. The candidate should have strong expertise in Scan Insertion, ATPG and MBIST, with good exposure to DFT architecture, timing, verification and production test flows.

Key Responsibilities

• Own and execute DFT implementation flows from RTL/netlist through signoff.
• Hands-on experience in Scan insertion, scan chain stitching and scan chain analysis.
• Develop and debug ATPG patterns for stuck-at, transition and other fault models.
• Perform ATPG coverage analysis and coverage improvement.
• Hands-on experience with MBIST insertion, configuration, pattern generation and debug.
• Experience with memory test algorithms, SRAM/ROM memories and memory repair.
• Work on scan compression / EDT, decompressor and compactor architecture.
• DFT clock definition, OCC insertion and clock/test-mode handling.
• Analyze and resolve DFT timing violations in collaboration with STA teams.
• Handle DFT constraints including SDC, test clocks, generated clocks and false/multicycle paths.
• DFT verification using simulation and debug of ATPG/MBIST patterns.
• Debug X-propagation, chain failures, pattern failures and coverage loss.
• Exposure to JTAG / IEEE 1149.1, IEEE 1500 and IEEE 1687 (IJTAG).
• Exposure to LBIST and hierarchical DFT is an added advantage.
• Support pre-silicon and post-silicon DFT debug and tester bring-up.
• Work closely with RTL, STA, synthesis, physical design, verification and ATE/test engineering teams.
• Develop automation scripts using TCL, Perl, Python and Shell.

Required Skills

• 6+ years of hands-on DFT experience.
• Strong knowledge of Scan, ATPG and MBIST.
• Experience with DFT insertion and signoff.
• Good understanding of ASIC/SoC design flow.
• Experience with tools such as Synopsys TestMAX/TetraMAX, DFTMAX, Siemens Tessent or Cadence Modus.
• Strong debugging and problem-solving skills.
• Good understanding of synthesis, STA and gate-level simulation.
• Experience with at least one or more successful ASIC/SoC tapeouts.

Good to Have

• Scan compression / EDT.
• LBIST.
• Hierarchical DFT.
• JTAG / IJTAG / IEEE 1500.
• SRAM repair / redundancy.
• Low-power DFT.
• Silicon bring-up and ATE debug.
• DFT methodology development.
• Python/TCL automation.
• Experience with advanced technology nodes.