Technical Manager DFT (Design for Test)

Technical Manager – DFT (Design for Test)

Location: Bengaluru

Experience: 12–16 Years

About the Role

We are looking for a highly technical DFT Manager to lead the architecture, implementation, and signoff of Design-for-Test solutions for next-generation SoCs targeting AI/ML, Data Center, Networking, Automotive, and High-Performance Computing applications.

This role requires a hands-on leader who can drive DFT strategy, manage a high-performing engineering team, influence silicon architecture decisions, and deliver world-class test solutions across complex multi-billion transistor designs.

What You'll D

• oLead DFT architecture, implementation, and signoff for complex SoCs and IPs
• .Define and drive chip-level DFT strategy including Scan, ATPG, MBIST, LBIST, Boundary Scan, Compression, and Silicon Bring-up
• .Own test coverage, test quality, diagnosis strategy, and manufacturing test readiness
• .Drive DFT planning from architecture through tape-out and production ramp
• .Collaborate closely with RTL, Verification, Physical Design, Product Engineering, and Silicon Validation teams
• .Review and optimize DFT architecture for coverage, test time, power, area, and manufacturability
• .Lead root-cause analysis of silicon failures and drive yield improvement initiatives
• .Establish scalable DFT methodologies, automation frameworks, and signoff flows
• .Build, mentor, and lead a high-performing DFT engineering team

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Minimum Qualificatio

• nsBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related fiel
• d.12–16 years of experience in DFT for complex ASIC/SoC design
• s.Proven experience leading DFT teams and delivering multiple successful silicon tape-out
• s.Strong expertise in DFT architecture, implementation, and signof

f.
Preferred Technical Expert

• iseDeep expertise in Scan Insertion, Scan Compression, ATPG, MBIST, LBIST, JTAG/IEEE 1149.x, Boundary Scan, and Test Diagnos
• is.Strong understanding of DFT architecture for CPU, GPU, AI Accelerators, Networking, Storage, and High-Performance So
• Cs.Hands-on experience with Tessent, Synopsys TestMAX/DFT Compiler, Modus, TetraMAX, SpyGlass DFT, and ATPG signoff flo
• ws.Expertise in test coverage analysis, fault grading, diagnosis, silicon debug, yield improvement, and manufacturing test flo
• ws.Strong understanding of RTL, Computer Architecture, Low-Power Design, CDC, Physical Design, STA, and SoC Integrati
• on.Experience with hierarchical DFT, chiplet-based architectures, multi-voltage designs, and advanced-node technologies (7nm/5nm/3nm preferre
• d).Proficiency in Tcl, Python, Perl, and automation-driven DFT methodologi