Job Requirements
At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
Technical Lead-Blk P&R
- The responsibilities will include several of the following, but not be limited to:
- Performing floor-planning and routing studies and implementation at block and full-chip level
- Push down the top-level floorplan and clock to Partition.
- IO Planning and bump planning
- Closely working with Package team and reaching Die file milestones
- Evaluate low power techniques and power reduction opportunities
- Perform clock distribution design and analysis
- Drive technical activities of physical design during technology readiness, design & execution
- In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes
- Should have experience in handling >1M instance count, 1 GHz frequency designs
- Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency
- Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)
- Experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
Work Experience
- Technical Lead-Blk P&R
- The responsibilities will include several of the following, but not be limited to:
- Performing floor-planning and routing studies and implementation at block and full-chip level
- Push down the top-level floorplan and clock to Partition.
- IO Planning and bump planning
- Closely working with Package team and reaching Die file milestones
- Evaluate low power techniques and power reduction opportunities
- Perform clock distribution design and analysis
- Drive technical activities of physical design during technology readiness, design & execution
- In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes
- Should have experience in handling >1M instance count, 1 GHz frequency designs
- Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency
- Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)
- Experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
