Technical Architect – DFT
Location: Bengaluru
Experience: 12–18 Years
Role Overview
We are seeking a highly experienced Technical Architect – DFT to drive architecture, implementation, and signoff of advanced DFT solutions for complex SoCs. The role demands deep expertise in scan compression, ATPG, MBIST, IJTAG, and hierarchical DFT methodologies across leading-edge process nodes.
Key Responsibilities
- Define and drive SoC/IP-level DFT architecture and implementation strategy.
- Lead Scan, EDT/Compression, MBIST, LBIST, OCC, and IJTAG (IEEE 1687) integration.
- Own ATPG generation, fault coverage closure, and pattern validation.
- Drive DFT signoff, silicon bring-up support, and failure diagnosis.
- Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for DFT convergence.
- Develop and automate DFT flows using Tcl, Perl, or Python.
- Mentor engineers and provide technical leadership across projects.
Technical Skills
- Strong expertise in Scan, Compression, MBIST, LBIST, ATPG, OCC, and Boundary Scan.
- Hands-on experience with Siemens Tessent and/or Synopsys DFT Compiler, TestMAX, TetraMAX.
- Solid understanding of IEEE 1149.1, IEEE 1500, IEEE 1687, and hierarchical DFT methodologies.
- Experience with low-power DFT, clocking architectures, and advanced-node SoC designs.
- Proficiency in Verilog/SystemVerilog and scripting languages (Tcl, Perl, Python).
- Exposure to silicon debug, yield enhancement, and manufacturing test flows is highly desirable.
Qualifications
- B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, or related disciplines.
- Proven track record of leading DFT architecture and delivering successful silicon for complex SoCs.
