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Synthesis/STA Engineer (Applications Engineering)

4-6 Years
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Job Description

  • Proficiency with STA, SDC
  • Proficiency with RTL, System Verilog
  • Strong understanding of front-end EDA design methodologies
  • Strong Perl, Tcl or Python scripting skills
  • Prior experience with logic synthesis tools is required
  • Prior experience using or supporting SDC tools would be a significant plus
  • Prior experience with RTL simulation, SVA would be a plus
  • Prior experience supporting front-end EDA tools would be a plus
  • Sound communication skills, verbal and written
  • Ability to produce product requirement documents
  • BS EE/CE. 4 years experience with STA/Synthesis

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Indian

About Company

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Job ID: 118199719