Synthesis Engineer

rtl development , Clp, Tcl, Python, Perl, Memory BIST insertion, UPF development, Low power checks, Synopsys Prime Time, Synthesis LEC, Cadence Conformal Low Power, clock gating, Genus Fusion Compiler, RTL Lint, Physical Design, Cadence Conformal LEC, Synopsys DCG, Constraints validation, DRC, power optimization flows, TCL script development, Dft, MemBIST

design optimization, Logic Synthesis, Physical-aware RTL-to-gate synthesis, CDC-related timing issues, Timing Closure, PPA optimization, Post-route timing analysis, Formal equivalence checking, SDC constraints, ECO implementation, MMMC timing analysis

Tcl Scripting, SDC constraints, Timing Constraints, Fusion Compiler, Synopsys Design Compiler, clock gating, LEC, low-power design, UPF, ECO flows

Tcl, Python, Perl, timing ECO generation, Timing Constraints, timing constraint validation, AOCV, timing convergence, UPF basics, cross-talk, STA fundamentals, noise process variation, UPF based static low power check, ASIC Back End flows, power optimization techniques, Signal Integrity, physical and UPF aware synthesis, POCV, power analysis