Sykatiya Technologies - RTL Design Engineer - ASIC/SoC
Sykatiya Technologies - RTL Design Engineer - ASIC/SoC
sykatiya technologies pvt ltd- Posted a month ago
- Over 100 applicants have applied
Job Description
Responsibilities
- Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
- Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
- Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
- Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
- Perform RTL Lint and work with the Designers to create waivers.
- Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults.
- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.
- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
- Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback.
More Info
Key Skills
Automation scripts
Gate Level Netlist
RTL Lint
RTL DFT Analysis
Logic Physical Synthesis
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