Static Timing Analysis | Synthesis Engineer

We are Hiring for a STA / Synthesis Engineer (Staff / Sr. Staff / Principal)

Location - Bengaluru

Role Summary

As a Staff/Sr. Staff/Principal STA/Synthesis Engineer at Velaura AI, you will own RTL-to-gate

synthesis, static timing analysis, and timing closure for next-generation AI and high performance computing silicon. You will be responsible for driving implementation quality, timing convergence, power optimisation, and sign-off readiness for complex compute, CPU, VPU, and low-power cores targeting advanced process technologies. You will work closely with RTL, architecture, DFT, physical design, CAD, verification, and product engineering teams to achieve aggressive Performance, Power, Area, and Cost targets. This is a highly visible technical role where you will influence synthesis strategy, timing closure methodology, constraint quality, ECO flows, and implementation best practices for complex ASIC/SoC designs.

Responsibilities

• Drive RTL-to-gate synthesis for complex compute, CPU, VPU, AI accelerator, and low-power cores using industry-standard synthesis tools.
• Own synthesis setup, constraints, optimization, quality checks, and netlist delivery for block-level and subsystem-level designs.
• Lead static timing analysis and timing closure activities across multiple modes, corners, voltage domains, and clock domains.
• Optimize designs for timing, power, area, and cost while meeting aggressive design targets and schedule requirements.
• Develop, validate, and maintain high-quality timing constraints, including full-chip, block-level, generated clock, false path, multicycle path, and interface constraints.
• Drive multi-mode multi-corner timing analysis, constraint management, timing debug, and convergence across all sign-off scenarios.
• Work closely with RTL, DFT, physical design, and verification teams to resolve timing, constraints, clocking, reset, DFT, and low-power implementation issues.
• Own timing sign-off readiness and ensure compliance with timing, power, signal integrity, and implementation quality requirements.
• Drive hierarchical timing closure across blocks, subsystems, and full-chip interfaces.
• Implement and optimize low-power design strategies including clock gating, multi-voltage domains, power-aware synthesis, and UPF/CPF-based power intent flows.
• Execute timing ECO flows for setup, hold, transition, capacitance, noise, and late-stage design closure.
• Support physical-aware synthesis, placement-aware optimization, and collaboration with physical design teams to improve timing and PPA correlation.
• Define and improve synthesis, STA, constraints, ECO, and timing closure methodologies for high-quality and efficient implementation.
• Evaluate and deploy EDA tools, flows, and automation to improve runtime, productivity, quality of results, and turnaround time.
• Develop scripts using Tcl, Perl, Python, or other languages to automate synthesis, STA, reporting, debug, and flow validation.
• Collaborate with geographically distributed teams and provide technical leadership in implementation, timing closure, and sign-off quality.