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Static Timing Analysis (STA) Engineer
Job Summary
The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.
Key Responsibilities
Methodology and Flow
Education
Technical Skills & Experience
Soft Skills
Ability to work effectively in a team environment and collaborate across different engineering disciplines.
Job ID: 151735169
Skills:
synopsys primetime , Usb, Tcl, Ethernet, Perl, Python, Pcie, DDR, CPF, EMIR, CXL, Design Compiler, STA Signoff, low-power UPF, Innovus Design Compiler, Timing ECO, Fusion Compiler, OCV, CTS, Sta, ICC2, MMMC, Si, PrimeTime SI, Cadence Tempus, SDC
Skills:
synopsys primetime , Tcl, Python, Perl, AOCV, place-and-route, timing exceptions, Extraction, CTS, OCV, clocking methodologies, SI noise analysis, Synthesis, MMMC methodologies, ECO implementation, POCV
Skills:
synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking