THE ROLE:
Help turn possibility into reality every day. At AMD, we push the boundaries of what is possible by delivering innovative, high-performance computing solutions across data center, AI, and advanced packaging technologies.
We are seeking a highly experienced SMTS Package Design Engineer to support complex package design execution. This role requires a self-driven technical expert who thrives in a fast-paced, dynamic, and high-pressure environment, and can deliver high-quality designs with speed, precision, and scalability.
The successful candidate will play a key role in advancing AMD's packaging methodologies by leveraging AI-driven design techniques, automation, and next-generation workflows to address the increasing complexity of heterogeneous integration and advanced packaging architectures.
THE PERSON:
The ideal candidate is an experienced package or silicon physical designer who:
- Demonstrates strong ownership and accountability across multiple programs
- Excels in fast-phase execution environments with competing priorities
- Applies AI/ML and automation to improve design productivity and quality
- Operates with minimal supervision while influencing cross-functional teams
- Balances deep technical expertise with strong collaboration and communication skills
KEY RESPONSIBILITIES:
Design Execution & Technical Leadership
- Lead end-to-end package design execution for complex products, ensuring performance, cost, quality, and schedule targets are met
- Handle multiple concurrent design programs in a fast-paced and high-pressure environment
- Develop substrate layouts, bump maps, and interposer designs for advanced packaging (2.5D/3D, chiplet-based architectures)
- Drive design decisions through close collaboration with SI/PI, mechanical, and SOC teams
Cross-Functional Collaboration
- Partner with internal engineering teams, OSATs, and substrate suppliers to deliver optimized solutions
- Interface with stakeholders to communicate design status, risks, and mitigation strategies
- Contribute to design reviews, signoff readiness, and tapeout processes
Methodology & Continuous Improvement
- Define and enhance package design methodologies, flows, and best practices
- Drive improvements in layout efficiency, reuse, and design standardization
- Mentor junior engineers and promote engineering excellence across the team
PREFERRED EXPERIENCES:
- Experience in designing complex substrate design or Silicon Bridge or Interposers
- Proven ability to execute in multi-project, fast-phased, and high-pressure environments
- Strong experience in advanced packaging technologies:
- 2.5D / 3D integration (e.g., interposers, chiplets)
- Hands-on experience with EDA tools such as:
- Cadence SIP / APD
- Synopsys 3DICC or equivalent
- Experience working with OSATs, foundries, and substrate vendors
- Solid understanding of Signal Integrity and Power Integrity fundamentals
ACADEMIC CREDENTIALS:
- Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or related field
LOCATION:
Singapore
