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Job ID: 149008893
Skills:
Perl, Python, Tcl, LVS DRC violations, Timing area and power constraints, Block-level place and route, P R flow development, CAD and physical design methodologies, Clock network guidelines, Physical design verification, Logic equivalency RTL2Synthesis, Physical Design, Synthesis2APR netlist, PPA optimization
Skills:
PERL, Tcl, Tk, Cadence Innovus
Skills:
synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, jitter, path-based analysis, false paths, Timing Closure, AOCV, skew
Skills:
redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning
Skills:
Backend Engineering, Python, LangChain, pgvector, LangFuse, AI System Design, Pinecone, LLM Integration, LangSmith, AI Safety Quality, LangGraph, OpenAI SDK, Data Pipelines for AI, Infrastructure DevOps, Weaviate, Claude SDK
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