Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementationfor SLM monitors realized through ASIC design flow.
Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics.
Developing Digital BE activities includes synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, routing and collaborating with the different functional teams to achieve optimal design solutions.
Post layout STA, timing & functional ECO development, timing signoff methodology at higher frequency IP designs closure.
Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff.
Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams.
Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products.
What You'll Need:
BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience.
Strong Physical design, physical verification, pre& post layout STA and EMIR/Power signoff experience, including SDC development, UPF/Mutlivoltage design development experience.
Experience in DRC, LVS, DFM cleaning and timing closure is mandatory.
Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk
Sound understanding of Physical design, Physical verification and STA and signoff concepts.
Experience in generating ECO for DRV cleaning and timing closure is mandatory.
Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/PT/PT-PX
Sound understanding of Physical design, STA and signoff concepts.
Proven track record of successful timing closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...)
Good understanding of OCV, POCV, derates, crosstalk and design margins.
Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required.
