Staff Engineer Design Verification

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking a highly skilled and independent Design Verification Engineer to join our RISC-V CPU team. In this role, you will be responsible for the block-level verification of high-performance Cache and Coherence units. You will lead the development of sophisticated UVM environments to ensure the quality and reliability of our next-generation IP solutions.

This role ishybrid, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have 8 + years of istrong hands-on experience with SystemVerilog and UVM and enjoy building verification environments from the ground up.
• You are comfortable driving complex DV efforts independently, from strategy definition to coverage closure.
• You have a solid understanding of RTL verification, debugging, and coverage analysis.
• You bring curiosity and strong problem-solving skills, with exposure to cache, interconnects, or memory systems being a plus.

What We Need

• Define comprehensive verification strategies and architect robust DV environments for block and sub-system level IPs.
• Develop reusable UVCs and execute constrained-random test plans to validate complex corner cases.
• Perform RTL-level functional verification, improve functional and code coverage, and debug complex failures.
• Collaborate closely with design and cross-functional teams to drive verification projects to completion.

What You Will Learn

• Deep hands-on exposure to cache pipelines, memory subsystems, and high-performance interconnects.
• Advanced verification techniques to improve efficiency, scalability, and reliability across IPs.
• Practical experience working with AXI/CHI protocols, cache coherence, and memory consistency models.
• End-to-end ownership of complex DV projects in a fast-paced, high-performance compute environment.