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Job ID: 153799665
Skills:
Perl, Debugging, Shell scripting, Python, Tcl, Uvm, Mixed-Signal Verification, systemverilog
Skills:
liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL
Skills:
test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors
Skills:
Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog
Skills:
liberty , Scripting, Tcl, python, Pcie, DDR, IO standards, bump map pattern definition, pad ring planning, RTL, Isp, EDA Tools, IO cell placement, PHY-level IO interfaces, Orbit IO, CXL, IO library cells, flow automation, lef, SERDES