Staff Engineer, ASIC Development Engineering

Company Description

SanDisk is uniquely positioned at the heart of the AI-driven data economy, with a focused portfolio centered on advanced NAND flash and SSD technologies that underpin cloud, enterprise, and hyperscale infrastructures. As AI workloads continue to explode in scale and complexity, the need for high-throughput, low-latency, and energy-efficient storage has become mission-criticalan area where SanDisk's technology leadership clearly stands out.

Now operating as a focused, independent storage company, SanDisk has sharpened its execution and innovation engine to serve the rapidly growing AI, data center, and edge markets. Its inclusion in the S&P 500 is a strong validation of both its operational maturity and its relevance as a core infrastructure player in the global technology ecosystem.

As AI increasingly moves from training to large-scale inferencing, storage plays a decisive role in system performance. Fast access to models, embeddings, and real-time data requires ultra-low latency, high endurance, and power-efficient storageparticularly in distributed and edge deployments. SanDisk's flash-based solutions are well aligned to enable efficient, scalable AI inferencing by minimizing data movement bottlenecks between compute and storage.

Driven by experienced leadership and a clear long-term vision, SanDisk is not just responding to the AI waveit is helping define the storage foundation on which next-generation AI systems will be built.

Job Description

Sandisk's ASIC team buildsstate-of-the-art memory controllersthat power world-class NAND Flash products used globally at massive scale. Design Enablement team enables the Technology, Methodology and Flows to the Mixed Signal IP team to deliver best in class products. As theMSIP CAD/Methodology Engineer, you will play a pivotal role in developing, and delivering robust MSIP Design methodologies oncutting-edge technology nodes, enabling best-in-classquality and productivity.

This role is ideal for a seasoned MSIP methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams.

Key Responsibilities

• Mixed-signal IP CAD and methodology development, covering schematic, layout, verification, and signoff flows.
• Architect and maintainend-to-end custom design methodologies, from transistor-level design through signoff-ready layouts.
• Drivelayout quality standards, including matching, symmetry, parasitic control, reliability, and manufacturability.
• Define and enforcephysical verification methodologies, including:
• DRC
• LVS
• PERC
• Reliability and signoff checks
• Own and evolvesignoff methodologiesfor mixed-signal IPs, includingEM/IR analysisand reliability verification.
• Work closely withcustom circuit designers and layout teamsto identify recurring issues and introduce automation, checks, and best practices.
• Collaborate withfoundry counterpartsto understand process-specific constraints, reliability requirements, and rule interpretations.
• Developcorrect-by-construction and shift-left flowsto catch issues early and reduce iteration cycles.
• Drivetool qualification, flow robustness, and productivity improvementsacross multiple IP programs.
• Mentor engineers and foster a culture ofquality, rigor, and innovationwithin the CAD/methodology team.
  

Qualifications

Requirements

• 3-5years of experiencein mixed-signal / analog design, custom layout, CAD, or methodology roles.
• Strong understanding of transistor-level circuit design, including device behavior, biasing, matching, noise, and variability.
• Hands-on experience withcustom layout designand a deep appreciation oflayout quality and its impact on circuit performance.
• Expertise inphysical verification and signoff, including:
• DRC, LVS, PERC
• EM/IR and reliability signoff tools
• Proven experiencearchitecting custom design and verification methodologiesfor mixed-signal IPs.
• Strong understanding ofinteractions between circuit design, layout parasitics, and signoff requirements.
• Proficiency inscripting and automationusingSVRF, SKILL, TCL, Python, and/or Perl.
• M.Tech / MS in VLSI Design, Microelectronics, or a related field (or equivalent industry experience).
  

Additional information

Desirable Skills

• Exposure toadvanced nodesand complex signoff requirements.
• Experience withmemory controllers or high-performance data-path designs.
• Prior experience applyingAI/ML in EDA or design automationis a strong plus.
• Strong communication and stakeholder management skills.
  
  

Additional Information

Desirable Skills

• Exposure to advanced nodes and complex signoff requirements.
• Experience with memory controllers or high-performance data-path designs.
• Prior experience applying AI/ML in EDA or design automation is a strong plus.
• Strong communication and stakeholder management skills.