Job Description
About the Role
The position involves design verification of next generation IP's /SoC's with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification.
Responsibilities
- :To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs
- .Leading a project for AMS requirements is a value add
- .Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tool
- sKnowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus
- .Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS
- )Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plu
- sFunctional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expecte
- dExperience working on AMS Verification on multiple SOC's or sub-system
- sWorking knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plu
- sCandidate should have ability to lead a project team, and work collaboratively in a multi-site development environmen
- tDelivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situation
- sCandidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows
- .Develop and execute top-level test cases, self-checking test benches and regressions suite
- sDeveloping and validating high-performance behavior model
- sVerifying of block-level and chip-level functionality and performanc
- eTeam player with good communication skills and previous experience in delivering solutions for a multi-national clien
- tTool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experienc
- eFluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc
- .Ability to extract simulation results, capture in a document and present to the team for peer revie
- wSupporting silicon evaluation and comparing measurement results with simulation
- sUVM and assertion knowledge would be an advantag
e
Experience Level: 10-15 years in Indust
ryEducation Requirements: Bachelor or Master's degree in Electrical and/or Computer Engineeri
ngMinimum Qualification
- s:Proficient in at least one of the following languages: Verilog, SystemVerilog, VerilogAM
- S.Strong understanding of analog circuits, digital design processes, and top-level integratio
- n.Basic knowledge of PMIC and DC-DC converter
- s.Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RT
- L.Proficient in Unix environment and shell scripting, with a basic understanding of Pytho
n.
Preferred Qualificatio
- ns:Mentoring ski
- llsExceptional problem-solving ski
- llsGood written and oral communication ski
lls
Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and
- fun.Equity Rewards (R
- SUs)Employee Stock Purchase Plan (E
- SPP)Insurance plans with Outpatient c
- overNational Pension Scheme (
- NPS)Flexible work po
- licyChildcare sup
port
