- Verification of complex ASIC chips and sub-systems using leading edge verification methodologies
- Define test plans, tests and verification methodology for block and chip level verification.
- Employ UVM/SystemVerilog based verification methodologies and use scoreboard, assertions, functional/code coverage, formal verification etc to reach verification goals.
- Take complete ownership for a complex feature verification and technically mentor & guide junior verification engineers.
- Define and implement improvements in verification flow and methodology.
- Gate level simulations and debug of large digital blocks and full-chip ASICs
- Support post-silicon validation activities of the products working with design, applications and test team.
Job Requirements:
- Bachelors or masters degree in Electrical or Computer Engineering with 7+ years of experience in digital verification.
- Expertise in Verilog, System Verilog, UVM, object-oriented programming, scripting and automation with Perl or Python.
- Firm understanding of constrained random functional verification, coverage, and assertions.
- Expertise in test plan development and development of verification environments from ground up.
- Extensive experience with verification of complex blocks, regressions and coverage closure.
- Experience with gate level simulations and debug.
- Excellent debugging, analytical and problem-solving skills.
- Strong inter-personal, teamwork and communication skills.
- Expected to be highly independent, proactive and result-oriented to achieve verification goals.
Preferred qualifications:
- Knowledge of Video (DisplayPort, CSI/DSI), PCIe, Ethernet, I2C, UART, SPI and Audio I2S protocols..
- Experience with lab silicon bring-up, validation and production test support.
- Experience in technically mentoring, coaching junior engineers.
