To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add.
In your new role you will:
- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools
- Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus.
- Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS)
- Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus
- Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected
You are best equipped for this task if you have:
- Experience working on AMS Verification on multiple SOCu2019s or sub-systems
- Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus
- Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment
- Independent in process usage, Enthusiastic learner and debug the routine issues
- Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations
- Bachelors or Masters in Electrical Engineering
- Independent in process usage, Enthusiastic learner and debug the routine issues
- Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations
