STA & Synthesis Architect

STA & Synthesis Architect

Location: Bengaluru

Experience: 10–16 Years

Role Overview

We are looking for an experienced STA & Synthesis Architect to drive timing and synthesis methodology for complex, high-performance SoCs. The role requires strong expertise in Static Timing Analysis, RTL Synthesis, timing closure and implementation optimization.

Key Responsibilities

• Define and drive STA and synthesis methodologies for complex SoC designs.
• Lead RTL-to-gate synthesis, constraint development and optimization for PPA.
• Own timing analysis and closure across multiple modes and corners.
• Develop and validate SDC constraints, timing exceptions and clocking strategies.
• Analyze and resolve setup, hold, max transition, max capacitance and clock-related violations.
• Drive timing correlation across Synthesis, P&R and sign-off STA.
• Work closely with RTL, Physical Design, DFT and Architecture teams to resolve timing and PPA challenges.
• Develop and improve synthesis/STA flows, automation and methodologies.
• Drive timing optimization across high-performance CPU, AI/ML, networking or complex SoC designs.
• Provide technical guidance on timing architecture, constraints and synthesis strategies.
• Lead technical reviews and mentor senior STA/Synthesis engineers.

Required Expertise

• 10–16 years of experience in STA, Synthesis and ASIC/SoC implementation.
• Strong hands-on expertise in Synopsys Design Compiler / Fusion Compiler and PrimeTime or equivalent.
• Deep understanding of STA concepts, SDC, MMMC, clocking, timing exceptions and OCV/AOCV/POCV.
• Strong understanding of RTL synthesis, logic optimization and PPA trade-offs.
• Experience with advanced technology nodes and complex SoCs.
• Strong scripting skills in Tcl, Python or Perl.
• Experience with timing sign-off and correlation with physical implementation.
• Strong architectural thinking, problem-solving and technical leadership skills.