STA Engineer

STA Engineer

Location: Bengaluru, India

Experience: 4–10 Years

Role

Drive Static Timing Analysis (STA) and timing closure for high-performance SoCs across advanced technology nodes. Own timing signoff from synthesis through tapeout while delivering optimal PPA.

What You'll Do

• Perform full-chip/block-level STA and timing signoff across MMMC scenarios.
• Drive setup/hold closure, ECO implementation, and timing convergence.
• Develop and validate SDC constraints, timing exceptions, and clock definitions.
• Analyze and resolve SI, Crosstalk, OCV/AOCV/POCV, CRPR, and timing violations.
• Collaborate with RTL, Synthesis, Physical Design, CTS, and DFT teams to achieve timing closure.
• Develop automation using Tcl/Python/Perl to improve STA productivity.

What You Bring

• 4–10 years of hands-on experience in ASIC/SoC Static Timing Analysis.
• Strong expertise in PrimeTime and/or Cadence Tempus.
• Deep understanding of MMMC, SDC, OCV/AOCV/POCV, CRPR, SI, Crosstalk, ECO, and Timing Signoff.
• Experience with advanced technology nodes (16nm/7nm/5nm/3nm).
• Good understanding of RTL, Synthesis, Physical Design, CTS, and Low-Power (UPF).
• Strong scripting skills in Tcl, Python, or Perl.

Preferred

• Experience with CPU, GPU, AI/ML, Networking, Mobile, or Automotive SoCs.
• Exposure to EM/IR and Physical Signoff is an added advantage.