STA Engineer

Job Title: STA Engineer

Experience: 5+ Years

Location: Bengaluru

Notice Period: Immediate to 30 Days Preferred

Job Description

We are looking for an experienced STA Engineer with 5+ years of hands-on experience in Full-Chip Static Timing Analysis (STA) and timing sign-off for complex SoC designs. The candidate should have strong expertise in timing closure, MMMC analysis, constraint development, and advanced technology nodes.

Key Responsibilities

• Perform block-level and full-chip STA and timing sign-off.
• Develop and validate SDC constraints for complex designs.
• Analyze and debug setup, hold, recovery, removal, and clock gating violations.
• Perform timing closure across all MMMC scenarios.
• Handle timing ECO generation and implementation.
• Work closely with RTL, Synthesis, DFT, Physical Design, and CTS teams to resolve timing issues.
• Perform SI-aware timing analysis and crosstalk debugging.
• Support low-power timing analysis using UPF/CPF methodologies.
• Drive sign-off activities and ensure timing closure before tape-out.

Required Skills

• Strong knowledge of Static Timing Analysis concepts.
• Hands-on experience in:
• Full-Chip STA
• Timing Sign-off
• MMMC Setup & Analysis
• SDC Constraint Development
• Setup/Hold Analysis
• Timing Closure
• ECO Generation & Validation
• Crosstalk and Signal Integrity Analysis
• Clock Domain Crossing (CDC) Analysis
• Low-Power Timing Analysis

EDA Tools

• Synopsys PrimeTime (PT)
• PrimeTime SI
• Tempus
• VC SpyGlass / CDC Tools
• ECO Tools (PrimeECO or equivalent)

Scripting Skills

• TCL (Mandatory)
• Perl/Python/Shell Scripting (Preferred)

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, ECE, VLSI, or a related field.
• Experience with advanced nodes (16nm/7nm/5nm/3nm).
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and teamwork abilities.