Job Location: Pune, Maharashtra
Exp: 4 to 10 years
Responsibilities:
- Lead the development and implementation of comprehensive clocking strategies for high-performance ICs.
- Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis.
- Stay up-to-date with the Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks.
- Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control.
- Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan.
- Collaborate with design engineers, layout engineers, and other physical design teams to address timing closure challenges.
- Mentor and coach junior engineers, fostering their growth and expertise in clocking, constraints, and STA.
- latest advancements in clocking methodologies, timing analysis tools, and industry best practices.
- Lead the evaluation and implementation of new tools and methodologies for improved timing closure efficiency.
- Develop and maintain comprehensive documentation for clocking, constraints, and STA practices within the team.
