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Job ID: 147546199
Skills:
C, Requirements Traceability, Test Plan Creation, Tcl, Verilog, System Verilog, Python, Perl, Microprocessor architecture, interconnect, Assertions, UVM methodology, Gate Level Simulation, Testcase creation, Directed and constrained random methodologies, Metric Driven Verification, Coverage closure, Formal verification methodologies, SoC Verification, Functional and code coverage
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