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Sr Staff Engineer- RTL Design

Sr Staff Engineer- RTL Design

Renesas
12-17 Years
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  • Posted 12 days ago
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Job Description

Responsibilities:

  • Lead RTL synthesis and constraints generation/validation for MCU SoCs to meet performance, power, and area targets
  • Develop and implement innovative methodologies and tools to improve design quality and engineering productivity
  • Act as the key interface between frontend and backend design teams, resolving hand-off and timing-related issues
  • Conduct detailed design reviews and provide feedback to peers and junior engineers
  • Collaborate with cross-functional teams to resolve design collateral issues and enhance overall PPA (Power, Performance, Area)
  • Support low power implementation flows and techniques
  • Perform formality checks to ensure RTL vs. netlist equivalence

More Info

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Key Skills

ASIC development flow

Constraints generation

About Company

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier.As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog Connectivity, and Power.