Go through the latest architecture changes happening at SOC and create test plans for the same.
Own the features from test planning, stimulus creation in assmebly /C/C++, creating cover points, checker/scoreboards and meet the mile stone criteria.
Validate tests scenarios at sub-system/SOC/emulation level.
Should be able to build test bench components for the test plan requirements.
Maintain or improve current test libraries to support SOC level testing.
support the features qualification from simulation/emulation and all down stream teams.
Provide technical support to other teams based on requirement.
Added advantage for having knowledge in: coherency, Memory/Datapath, RAS, virtualization, CXL, Interrupts, Secure access etc.,
PREFERRED EXPERIENCE:
Good at Assembly/C/C++
Good in digital design/ wave form debugs using verdi or similar EDA tools.
Familiarity with System Verilog and modern verification libraries like UVM
Experience/Background on Computing architecture is added advantage.
ACADEMIC CREDENTIALS:
Bachelors or Master's degree in computer engineering/Electrical Engineering with 4+ years of experience
