Sr. Silicon Design Engineer

• Setup ASIC QA flows for RTL design quality checks.
• Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.
• Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
• Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.
• Checking the flow errors, design errors & violations and reviewing the reports.
• Debugging CDC, RDC issues and come up with the RTL fixes.
• Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.
• Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.
• Flows or Design porting to different technology libraries.
• Generating RAMs based on targeted memory compilers and integrating with the RTL.
• Running functional verification simulations as needed.

Job Requirements:

• B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience
• ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
• Digital design and experience with RTL design in Verilog/SystemVerilog
• Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
• Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces.
• TCL, Perl, Python scripting
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