Sr Principal Product Validation Engineer
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Job Description
- The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
- Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
- Experience in process automation with scripting.
- Experience with SystemVerilog, C++, UVM.
- Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
- Experience designing and implementing complex functional verification environments is required.
- Knowledge of protocols like PCIe, USB3/4, DP an added advantage.
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Date Posted: 29/05/2025
Job ID: 115750253
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About Company
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. For six years in a row, Fortune Magazine has named Cadence one of the 100 Best Companies to Work For. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health. We pride ourselves on creating and sustaining a company culture, that drives innovation and business success. Cadence is recognized as a Great Place to Work around the world, including as one of the Fortune “100 Best Companies to Work For” over the last six years.
Last Updated: 29-05-2025 10:05:46 AM
