Sr Principal Design Engineer

Key Responsibilities

• Own complete DFT implementation for assigned projects
• Define test architecture and identify required RTL modifications for DFT
• Perform scan insertion, low-power CLP checks, and logical equivalence checking (LEC)
• Develop timing constraints for test mode timing closure
• Perform scan and ATPG for various fault models
• Implement and verify boundary scan, ACJTAG, IEEE 1500, and IEEE 1687 (iJTAG) standards
• Run zero-delay and timing-aware simulations; debug issues across all DFT aspects
• Support post-silicon bring-up activities
• Collaborate with customers and support marketing & pre-sales teams on DFT solutions
• Work on high-speed and low-power design projects, ensuring test coverage and manufacturability