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Job Title: Sr Principal Design Engineer
Location: Noida
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
Job Summary:
The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers. The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions. The role will require customer interactions including pre and post-sales activities, DV methodology review and customer support.
Job responsibilities:
Experience and Technical Skills required:
Qualifications
Behavioral skills required
Job ID: 104487021
Skills:
SAS, Spi, Usb, Sata, Ethernet, Pcie, formal verification, Emulation qualification, Design Verification, UFS, MIPI, CCIX, UVM testbench development, I3C, CXL, HDMI
Skills:
Pcie, Spi, SAS, Usb, Sata, Ethernet, formal verification, Uvm, Emulation qualification, Design Verification, UFS, MIPI, CCIX, I3C, CXL, HDMI
Skills:
C, Tcl, Verilog, System Verilog, Python, Perl, Constrained random methodologies, Assertions, UVM methodology, Microprocessor architecture, Metric Driven Verification, Formal verification methodologies, SoC Verification