debugging complex IP designs, UVM methodology, test plan reviews, testbench development, systemverilog

Debugging, Regression Testing, Test Planning, Design Verification, IP Verification, systemverilog, Uvm, Testbench Development, Verification Architecture, Simulation, Coverage Closure

Ovm, automation, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification