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Sr. Design Verification Engineer - IP
Job Summary
We are seeking a
Senior Design Verification Engineer (IP DV) to verify complex, reusable
HighPerformance Computing (HPC) IP blocks used across multiple SoC programs. The role requires strong ownership of IPlevel verification, deep understanding of protocols and microarchitecture, and the ability to build scalable, reusable verification environments that support integration into larger SoCs.
The role also emphasizes adoption of
AIassisted verification techniques to improve debug productivity, regression efficiency, and verification quality for performancecritical IPs.
The ideal candidate is handson, detailoriented, and comfortable working closely with IP design and architecture teams to deliver highquality, productionready IPs.
Key Responsibilities
- Own IPlevel functional verification from specification review to signoff for HPCclass IPs
- Develop comprehensive IP verification plans, including corner cases, stress, and error scenarios
- Build reusable SystemVerilog / UVMbased verification environments for performancecritical IPs
- Develop UVM agents, sequences, scoreboards, and coverage models aligned with IP reuse goals
- Create directed and constrainedrandom tests targeting IP functionality, configuration space, and protocol compliance
- Drive functional, code, and assertion coverage closure at IP level
- Verify multiple configurations, modes, and parameterizations, including highthroughput and concurrency scenarios
- Perform detailed debug of RTL and testbench issues, working closely with IP designers
- Leverage AIassisted verification techniques (e.g., log analysis, regression triage, debug acceleration, coverage insights) to improve verification efficiency
- Ensure verification collateral is clean, reusable, and welldocumented for downstream SoC teams
- Review IP specifications, microarchitecture documents, and RTL for verification completeness
- Support IP release, handoff, and integration by SoC verification teams
- Mentor junior DV engineers and promote best practices, including adoption of productivityenhancing AI tools
Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field
- 46 years of handson Design Verification experience, primarily at IP level
- Strong expertise in SystemVerilog and UVM methodology
- Solid understanding of digital design and microarchitecture concepts
- Proven experience with assertionbased verification (SVA)
- Strong knowledge of functional and code coverage techniques
- Experience verifying configurable, reusable, HPCclass IPs
- Strong debug skills using industry simulators (VCS, Xcelium, Questa, etc.)
Preferred / NicetoHave Skills
- Experience verifying HPC or performancecritical IPs (data paths, fabrics, accelerators, memory or interconnect IPs)
- Experience verifying standard IP protocols such as:
- AMBA (AXI, AHB, APB, ACE)
- PCIe, USB, DDR, or interconnect fabrics
- Exposure to AIbased / MLassisted verification tools or flows, such as:
- AIassisted log analysis and failure triage
- Intelligent regression analysis or coverage gap identification
- Debug productivity tools leveraging data analytics or pattern recognition
- Experience with parameterized IPs and multiple operating modes
- Knowledge of lowpower features (clock gating, power states, UPF/CPF)
- Exposure to formal verification at IP level
- Scripting skills in Python, Perl, or Shell for regression, automation, and AIassisted workflows
- Experience delivering IPs used across multiple SoC programs
Soft Skills
- Strong sense of ownership and accountability
- Ability to work independently on complex, performancesensitive IPs
- Clear communication with design, architecture, and SoC teams
- Mentoring mindset and collaborative attitude
What We Offer
- Opportunity to work on cuttingedge silicon products
- High ownership and technical growth
- Collaborative and learningoriented engineering culture
- Competitive compensation and benefits
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.
This posting is for an existing vacancy.
