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Position Summary
About Samsung Semiconductor India Research (SSIR)Role and Responsibilities
Will be part System Architecture and Design team and primarily responsible for IP/BLK level RTL integration and design of IP/glues/wrappers which involves complex high-speed protocol integration and support cross-functional teams (DV, DFT, PD).
Shall be responsible for handling the collaterals/reviews of cross-functional teams such as (but not limited to) i) Test plan/coverage reviews ii) Synthesis/Constraints QC iii) DFT insertion, HIP, SCAN strategies and QC at RTL level et al
Required Skills:
.Hands on experience in Front end RTL design, Integration, architecture, coding at IP Level.
. Domain Experience in the field of High Speed Serdes design is preferred. (Any one or more of following sub-domains)
1)The domains include : Storage (USB, UFS), High-Speed (PCIe, Ethernet), Display/Multi-media (CSI, DSI, eDP), Memory (LPDDR, HBM)
2) Good protocol understanding on standard interfaces such as : MIPI (CD, M-PHY), DFI Protocols and AMBA
. Hands-on experience on tools - LINT/VCLP/CDC/RDC/SYNTHESIS/Meggalan are must have skills.
. Should be able to handle - Design Constraints (SDC) at IP/BLK or flat level and respective QC flows.
. Additional tool knowledge on AFL/XPROP/DFT added advantage
. Good scripting skilss - Any scripting language (Perl, Python, TCL)
Skills and Qualifications
Experience - 4 to 7 years
Qualifications
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltdis dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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Samsung R&D Institute India-Bangalore (SRI-B) is the largest R&D Center outside of South Korea and a key innovation hub in the Samsung group.
Job ID: 143894885
Skills:
static timing analysis, Synthesis, Front End SoC quality efficiency guardrails, SoC integration, low-power design architecture verification, 6G Radio Solutions, clock domain crossing, Soft Radio SOCs, Rtl Design, 5G, Optimization Techniques, formal equivalence checking, low-power design
Skills:
Pcie, Verilog, Ethernet, Debugging, Scripting, Python, Tcl, UCIe chiplet interconnects, digital design fundamentals, high-speed IO protocols, systemverilog, Rtl Design, CXL, micro-architecture, low-power design techniques
Skills:
Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, micro-architecture, System-Verilog, SOC design, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB
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