THE ROLE:
As a PD Manager, you will drive Physical design implementation and execution for next generation SOCs. You will manage PD team for end-to-end PD execution. You will work closely with the SOC architects, Physical design architects/leads, Design leads, IP teams to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective. The SOCs are based off the most complex process technologies It's a great opportunity to join the talented team that is well-invested in the implementation of futuristic designs in advanced process nodes.
THE PERSON:
You will be responsible for driving a team of silicon design engineers for the successful delivery of project tape-outs from RTL-GDS. You will use your knowledge of Physical design to lead a complete set of Backend activities, Specifically PnR, timing, verification and signoff including IP integration and full-chip aspects. This position requires a detail-oriented candidate who can drive a larger PD team on solutions across different PD domains. Leader with strong self-driving ability and winning attitude. The person should have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.
KEY RESPONSIBILITIES:
- Lead Physical design team for implementation and convergence of highly complex multi-million gate tiles, subchip and SOC full chip.
- Responsible for delivery of GDS starting from RTL including Signoff and physical verification.
- Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA.
- Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows.
- Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle.
- Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology.
- Strong interpersonal skills to work across teams in different geographies.
- Provide technical direction, guidance, and Support to the engineering team.
- People management, goal setting, assessment, calibration, appraisal and improvement plan.
PREFERRED EXPERIENCE:
- Experienced PD professional with 18+ years of industry experience in managing Physical design execution across RTL to GDSII, PnR, STA, Physical verification, Timing signoff to tapeout.
- Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification.
- Well-versed with Physical Design verification signoff techniques such as Formal equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc.
- Excellent presentation and inter-communication skills.
Qualifications:
- B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
- 15+ years of experience in PD execution.
- Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 2 SOC tape-outs.
- Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools.
