Job description

 About The Role  

In this position, you will be responsible for managing and working on all aspects of STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to:

Design and Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous and asynchronous paths, Clock domain crossing issues.

Understanding and debugging extraction issues, deciding timing signoff modes and corners, Design margins, Hierarchical timing including IO budgeting for partitions.

Drive the designs to timing closure, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff and quality checks.

You will also be part of debug/troubleshoots for a wide variety of tasks up to and including difficult/critical design issues and proactive intervention, as required.

 Qualifications 

EducationB.Tech. or M.Tech. in Electrical/Electronics Engineering with 10-14 years of experience.PreferenceMaster's Degree in Electrical/Electronics Engineering with VLSI/microelectronics specialization, with 10+ years of experience in STA.Key

Skills:

In-depth knowledge and hands-on experience with the overall silicon implementation flows and methodologies such as STA, Synthesis, Clocking is required. Good understanding and exposure of overall Timing closure cycle in SoC.

Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT/ETS).

Skill in Synopsys tools (PT/DC) and exposure to ICC will be an added advantage.

Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs.