SoC Front-End Design & Signoff Engineer

Amlogic is a global leader in fabless system-on-a-chip (SoC) solutions, powering multimedia consumer devices such as OTT/IP set-top boxes, Smart TVs, and Smart Home products. The company combines advanced media processing engines with cutting-edge CPU and GPU technologies to deliver optimized performance, cost efficiency, and energy savings. Amlogic supports rapid product development through turnkey solutions for Android and Linux platforms, catering to top pay-TV operators, OEMs, and ODMs. Founded in Silicon Valley, Amlogic operates globally with offices in Mountain View (HQ), Bangalore, Seoul, Shanghai, Singapore, Tokyo, London, Milan, Munich, and Novi Sad.

We are looking for an experienced engineer to join our team working on a high-performance networking SoC.

Responsibilities

• Drive SoC-level lint, CDC and RDC closure.
• Ensure RTL synthesis readiness and resolve synthesis issues.
• Develop and review timing constraints.
• Analyze timing reports and identify RTL critical paths.
• Work with RTL and backend teams on timing improvements.
• Review clock/reset architecture and crossing schemes.
• Manage technical waivers and front-end signoff status.
• Automate checks and reports using Tcl, Python or shell scripting.

Required Skills

• 5+ years of relevant ASIC/SoC experience.
• Strong Verilog/SystemVerilog knowledge.
• Hands-on experience with lint, CDC, RDC and synthesis tools.
• Good understanding of STA and SDC constraints.
• Experience with multi-clock and multi-reset SoC designs.
• Knowledge of synchronizers, asynchronous FIFOs and reset sequencing.
• Experience debugging RTL timing and synthesis issues.

Experience with SoC tapeout, networking SoCs, AXI, Ethernet, DMA, SRAM or DDR is preferred.