SoC Design Verification

Experience:

510 years in SoC Verification withexpertisein CPU DV and Bus Interconnects.

Responsibilities:

• Perform SoC DV and CPU DV for complex architectures.
• Develop scalable test benches (BFM, Scoreboard, Checkers, Monitors) inSystemVerilogand UVM.
• Create tests, functional coverage models, andSystemVerilogassertions.
• Debug issues related to memory architecture (DRAM, Cache, MMU), AXI, PCIe, DDR/HBM.
• Collaborate with design teams to ensure verification completeness.

Technical Skills:

• Excellent in SystemVerilog (SV) and UVM.
• Strong knowledge of AMBA protocols, ARM v8/v9, RISC-V, x86 architecture.
• Proficient in OOP/C++, Python scripting.
• Excellent debugging skills.