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Key Responsibilities
Required Qualifications
Job ID: 148878061
Skills:
rtl development , Static Timing Analysis, Verilog, synthesis flows, systemverilog, subsystem design, Cadence Tools, cdc, primetime, AHB, linting, APB, Axi, RDC, AMBA protocols, spyglass
Skills:
C, Uvm, Rtl Design, systemverilog, Basic Verification
Skills:
Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools
Skills:
C, Uvm, Rtl Design, systemverilog, Basic Verification
Skills:
Python Scripting, PrimeTime or equivalent tools, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog
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