Search by job, company or skills

best nanotech

Soc Design Engineer

Save
  • Posted 23 hours ago
  • Be among the first 10 applicants
Early Applicant

Job Description

Key Responsibilities

  • Design and integrate ARM-based subsystems derived from Arm Corestone reference systems into complex SoCs
  • Develop, modify, and integrate RTL (Verilog/SystemVerilog) for CPU subsystems, AMBA interconnects, memory controllers, and peripheral IPs
  • Collaborate with architecture teams on micro-architecture updates, feature definition, and performance goals
  • Work closely with verification teams to debug functional issues and achieve coverage closure
  • Support synthesis, STA, CDC/RDC, and handoff to physical design teams
  • Participate in design reviews, documentation, and subsystem bring-up for simulation, emulation, FPGA, and early silicon
  • Contribute to methodology improvements for scalable subsystem integration and reuse

Required Qualifications

  • Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering
  • 3–5 years of hands-on experience in SoC or subsystem RTL design
  • Strong understanding of ARM architecture and AMBA protocols (AXI, AHB, APB)
  • Practical experience with Arm Corestone reference designs or equivalent ARM-based subsystems
  • Solid background in ASIC front-end design flows (RTL development & integration)
  • Experience with Static Timing Analysis (PrimeTime / Cadence tools)
  • Hands-on exposure to CDC/RDC, linting, and synthesis flows (SpyGlass or equivalent)
  • Strong debugging skills across simulation, lint, CDC, and synthesis environments
  • Ability to work effectively in a cross-functional, fast-paced engineering environment

More Info

Job Type:
Function:
Employment Type:

About Company

Job ID: 148878061

Similar Jobs

Hyderabad, India

Skills:

rtl development Static Timing AnalysisVerilogsynthesis flowssystemverilogsubsystem designCadence ToolscdcprimetimeAHBlintingAPBAxiRDCAMBA protocolsspyglass

Hyderabad, India

Skills:

CUvmRtl DesignsystemverilogBasic Verification

Hyderabad, India

Skills:

Python ScriptingASIC design flowCircuit timing STAC embedded experienceDigital DesignLow power digital design and analysisRTL design in Verilog SystemVerilogASIC design in sub-20nm technology nodesPrimeTime or equivalent tools

Hyderabad, India

Skills:

CUvmRtl DesignsystemverilogBasic Verification

Hyderabad, India

Skills:

Python ScriptingPrimeTime or equivalent toolsASIC design flowASIC design in sub-20nm technology nodesLow power digital design and analysisDigital DesignC embedded experienceCircuit timing STARTL design in Verilog SystemVerilog