You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
- RTL to GDS2 flow
- Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
- Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
- Identify and implement opportunities for improving PPA
PREFERRED EXPERIENCE:
- 12+ years of professional experience in physical design, preferably with high performance designs.
- Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
- Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
- Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
- Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
- Experience in STA, full chip timing
- Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl.
- Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
- Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm
- Excellent physical design and timing background.
- Good understanding of computer organization/architecture is preferred.
- Strong analytical/problem solving skills and pronounced attention to details.
