SMTS Silicon Design Engineer

• Implementation and verification of DFT architecture and features.
• Scan insertion and ATPG pattern generation.
• ATPG patterns verification with gate-level simulation.
• Test coverage and test cost reduction analysis.
• Post silicon support to ensure successful bring up and enhance yield learning.

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (e.g., IEEE1500, JTAG 1149.x, Scan, memory BIST etc.).
• Experience with Mentor TestKompress and/or Synopsys Tetramax/DFTMAX.
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.