Passionate about firmware development on bare-metal or close to bare-metal environment. Ability to look at the big picture , architect solutions that are optimal and scalable, and document them concisely. Should be a good team player with a collaborative can-do attitude. Strong knowledge of computer architecture and low-level programming in C.
KEY RESPONSIBILITIES:
- Developing, porting, debugging, and documenting core firmware support for various DRAM technologies including DDR5, LPDDR5/5x RDIMM, LRDIMM, 3DS, etc., on AMD Desktop, Mobile, and Enterprise SoCs.
- Supporting emulation/simulation teams during pre-silicon phase to validate memory hardware and firmware.
- Working closely with hardware validation teams to optimize memory signal integrity, achieve highest possible performance and robust feature support.
- Assist memory validation teams with debug from initial power-on to achieve full functionality of all features in a timely manner.
- Developing custom memory firmware features for internal and external customers.
- Engage with technical leads to understand firmware scope and work on implementation to meet schedules and milestones.
- Work with internal and external teams to ensure highest level of quality and satisfaction throughout firmware lifecycle.
- Must be well-organized, technically oriented, and a self-starter with a demonstrated ability to work collaboratively and coordinate activities with geographically distributed technical teams.
- Desire to work and succeed on fast-paced and highly dynamic environments
QUALIFICATIONS:
Bachelor s or Master s degree (preferred) in Computer Science, Computer Engineering, Electrical Engineering, or equivalent with 10-15 years of experience
PREFERRED EXPERIENCE:
- Good understanding of firmware development cycle, integration and verification/validation for pre-si and post-si for SoC designs.
- Expertise in low-level C programming debugging for embedded systems.
- Ability to methodically root-cause complex failure mechanisms at the IP, subsystem and/or system level.
- Prior experience and/or exposure to testing platforms (Simulation and/or Emulation)
- Prior involvement in board, processor, or ASIC bring-up.
- Solid understanding of memory industry standards and technologies such as JEDEC, SPD Data, I2C/I3C, DDR4/5, LPDDR4/4x/5/5x UDIMM, RDIMM, LRDIMM, 3DS, ECC, Mode Registers, Self-Refresh, etc.
- Experience with or knowledge of DRAM Initialization/training algorithms, memory timings, addressing, overclocking, etc.
- Experience in debugging memory initialization and training issues.
- Experience in hardware/software interfaces and debugging sophisticated issues in CPU and firmware using JTAG, source code debuggers and other tools.
- Experience with source control systems including git/gerrit
- Excellent written and verbal communication and presentation skills.
