Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital reasoning design principles, RTL design concepts, and languages like Verilog or SystemVerilog.
- Experience with reasoning synthesis techniques to optimize RTL code, performance and power and design techniques.
- Experience in implementing system-on-chips (SoCs), subsystems, and sub-wrappers.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache.
- Experience with ARM based SoC, Debug (e.g., coresight).
- Knowledge of design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and System on a chip (SOC) architecture.
- Knowledge of cross-domain including domain validation, design for testing, physical design, and software.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will develop subsystems as part of the TensorG chipset. You will be coding, debugging and running simulations, and working with the Physical Design and Emulation teams during the development process. You will support hardware users by collaborating with teams outside the silicon group which includes supporting production software teams in development and debug collaborations.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities
- Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
- Participate in test plan and coverage analysis of the block and Application-Specific Integrated Circuit (ASIC)-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
- Work on the Module Design and integration activities including plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
